1. Field of the Invention
This invention relates to a data transformation device, and more specifically, to a data transformation device especially used for a rotation processing of image data.
2. Description of Related Art
An example of the prior art image data rotation processing is shown in FIGS. 1 to 3. FIG. 1 shows the prior art data transformation device used for the rotation process of image data of "n" bits.times."n" bits (where "n" is integer not less than 2). FIG. 2 shows a detail circuit of a RAM (Random Access Memory) cell marked with circles in FIG. 1, and FIG. 3 shows a detail circuit of a RAM cell not marked with circles in FIG. 1.
In the data transformation device of the prior art, the data is written in the following way: For example, the address line 401-n becomes "H" (high logical level) by an address selecting decoder 403, and the address line 401 of RAM cells 400-n0 to 400-nn becomes "H". In this case, the data of 402-li to 402-ni are written in RAM cells 400-n0 to 400-nn by the data line 405 and 406. On that time, the address line of RAM cells 400-n0 to 400-nn becomes "H", because the address line 401 and the address line 402 of the RAM cells 400-n0 are connected each other. But, the data of RAM cells 400-00 to 400-n0 are not destroyed because the data line 403 and 404 are precharged by a precharge signal 410.
Similarly to the case of data writing, the data is read by the following way that, as an example, the address line 401-n becomes "H" by the address selecting decoder 403, and one of the selected address line 401 of RAM cells 400-n0 to 400-nn of RAM cells becomes "H" and the address line 402 of RAM cells 400-00 to 400-n0 becomes "H". On that time, the data of RAM 400-n0 to 400-nn are read into the data line 405 and 406.
And in a time of the rotation signal 411 of "H", data of the data line 403 and 404 are issued to 402-lo to 402-n0, and in a time of the rotation signal 411 of "L" (low logical level), data of the data line 405 and 406 are issued to 402-lo to 402-n0.
Further, the other image data processing system for rotating image data is also shown Japanese Patent Application Laid-open No. JP-A-4-33178. It is the way that the CPU divides image information into K pixels=L columns of image information groups to rotate by an arbitrary degree by rectangular unit the pixel information on a work memory by each pixel unit by an arbitrary degree by rectangular unit. And then, It issues successively pixel of the pixel information group by the group unit into L image information latch circuits of K bits allocated in I/O address space of CPU. And, the same bits of outputs of the L circuits of the K bits of image information latch circuit are connected to the input and successively read from the K rotation gate circuits of L bits allocated in I/O address space CPU. And thereafter, It writes the image information which is divided the image information group by the group unit into the block rotated of an arbitrary angle by a rectangular unit.
The above mentioned data transformation device of prior art uses special RAM cells composed of 8 transistors, and it needs 2 systems of address line and data line. So, it causes a problem that the circuit scale becomes great. And also, there is the other problem that the wire length is long and its critical delay becomes great.
On the other hand, the other image data processing system for rotating image data is shown in Japanese Patent Application Laid-open No. JP-A-4-33178. but it needs circuits for the rotation of image data having image information latch circuits and rotation gate circuits. So it also causes a problem that its circuit scale becomes great.